Friday, August 18, 2006

kernel start up -blackfin arch

mach-bf537/head.S:

.text

ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
R0 = 0x36;
SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd
Bit)*/
/-------------------------------------------------------
SYSCFG: Only three settings

SYSCFG[2]: SNEN - self-nesting interrupt enable
SYSCFG[1]: CCEN - cycle count
SYSCFG[0]: SSSTEP - Supervisor Single Step

--------------------------------------------------------/

R0 = 0;

/*Clear Out All the data and pointer Registers*/
R1 = R0;
R2 = R0;
R3 = R0;
R4 = R0;
R5 = R0;
R6 = R0;

P0 = R0;
P1 = R0;
P2 = R0;
P3 = R0;
P4 = R0;
P5 = R0;

LC0 = r0;
LC1 = r0;
L0 = r0;
L1 = r0;
L2 = r0;
L3 = r0;

/*Clear Out All the DAG Registers*/
B0 = r0;
B1 = r0;
B2 = r0;
B3 = r0;

I0 = r0;
I1 = r0;
I2 = r0;
I3 = r0;

M0 = r0;
M1 = r0;
M2 = r0;
M3 = r0;

/* Turn off the icache */
p0.l = (IMEM_CONTROL & 0xFFFF);
p0.h = (IMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
/--------------------------
Disable ICPLB
---------------------------/

/* Anamoly 05000125 */
CLI R2;
SSYNC;
[p0] = R0;
SSYNC;
STI R2;

/* Turn off the dcache */
p0.l = (DMEM_CONTROL & 0xFFFF);
p0.h = (DMEM_CONTROL >> 16);
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/----------------------------
Disable DCPLB
------------------------------/

/* Anamoly 05000125 */
CLI R2;
SSYNC;
[p0] = R0;
SSYNC;
STI R2;

/* Initialise General-Purpose I/O Modules on BF537 */
/* Rev 0.0 Anomaly 05000212 - PORTx_FER, PORT_MUX Registers Do Not
accept "writes" correctly: */
p0.h = hi(PORT_MUX);
p0.l = lo(PORT_MUX);
R0.L = W[P0]; //Read
SSYNC;
R0 = (PGDE_UART | PFTE_UART)(Z);
W[P0] = R0.L; //Write
SSYNC;
W[P0] = R0.L; /* Enable both UARTS */
SSYNC;

p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
R0.L = W[P0]; //Read
SSYNC;
R0 = 0x000F(Z);
W[P0] = R0.L; //Write
SSYNC;
W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and
UART1 */
SSYNC;

p0.h = hi(EMAC_SYSTAT);
p0.l = lo(EMAC_SYSTAT);
R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
R0.l = 0xFFFF;
[P0] = R0;
SSYNC;

/*Initialise UART*/
p0.h = hi(UART_LCR);
p0.l = lo(UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;

p0.h = hi(UART_DLL);
p0.l = lo(UART_DLL);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;

p0.h = hi(UART_DLH);
p0.l = lo(UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;

p0.h = hi(UART_GCTL);
p0.l = lo(UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;

/* Initialize stack pointer */
sp.l = lo(INITIAL_STACK);
sp.h = hi(INITIAL_STACK);
fp = sp;
usp = sp;

/*Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM*/
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
call start_dma_code;

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