A JTAG interface is a special four/five-pin interface added to a chip,
designed so that multiple chips on a board can have their JTAG lines
daisy-chained together, and a test probe need only connect to a single
"JTAG port" to have access to all chips on a circuit board. The
connector pins are
1. TDI (Test Data In)
2. TDO (Test Data Out)
3. TCK (Test Clock)
4. TMS (Test Mode Select)
5. TRST (Test ReSeT) optional.
Since only one data line is available, the protocol is necessarily
serial like SPI. The clock input is at the TCK pin. Configuration is
performed by manipulating a state machine one bit at a time through a
TMS pin. One bit of data is transferred in and out per TCK clock pulse
at the TDI and TDO pins, respectively. Different instruction modes can
be loaded to read the chip ID, sample input pins, drive (or float)
output pins, manipulate chip functions, or bypass (pipe TDI to TDO to
logically shorten chains of multiple chips). The operating frequency of
TCK varies depending on the chip, but it is typically 10-100 MHz
(100-10ns per bit).
The hardware controller communicates serially with the JTAG-compliant
device through the TAP controller and uses the TCK and TMS inputs to
clock in state-machine commands.
These three TAP instructions manipulate the data:
• SAMPLE/PRELOAD—Used to either SAMPLE the data currently contained in
the BSCs, or to PRELOAD data into the BSCs.
• EXTEST—Performed when the BSCs attached to the JTAG compliant device
input pins act as sensors while the BSCs attached to output pins
propagates data to interconnecting devices. The interconnecting devices
may or may not be JTAG-compliant.
• BYPASS—Reduces the BSC shift path through the device to a single bit
register. For example, if a device contains 401 BSCs and the BYPASS
instruction is executed, the BSCs reduce to one for that device.
Program Flash Memory via JTAG
Engineers perform OBP by serially shifting data through the BSR and
latching the data into the BSCs. After the appropriate data is loaded
into the BSCs, the EXTEST instruction is used to propagate the BSC
contents to the Flash
memory. For instance, if the JTAG-compliant device contains 224 BSCs,
224 TCKs are used to clock in each bit of data. This represents one BSR
Each series of BSR shifts outputs one logical state, either high or low,
to the Flash memory. Each data bit is clocked in on the rising edge of
TCK, then the data bit is latched into the BSCs. After completely
loading the BSC with all data bits, the EXTEST instruction is used to
perform a BSR shift, which outputs data to the Flash memory. Each BSR
shift increases programming time; minimizing the number of BSR shifts
enables faster programming times.